Career Profile
CAD engineer with over 6 years of expertise in digital design timing sign-off methodology, on-chip variation (OCV) aware timing analysis. Specialized in physical variation aware STA methodologies, estimating design margins. Currently researching design-tech co-opt. (DTCO) and enhance timing estimation accuracy in STA due to silicon-to-model mis-correlation at the design level.
Experiences
DTCO: Lead the development of variation aware STA flows for 4nm, 3nm and 2nm technology nodes
- Developed a silicon-to-model mismatch aware STA methodology.
- Built STA flows accounting for interconnect skew, Vmin weak path analysis
- Developed aging-aware STA methodology Supported timing closure by analyzing weak paths at STA, in collaboration with SOC designers. Participated in library characterization committee at Samsung Foundry; defined parameter perturbation ranges for timing, power sensitivity libraries.
DTCO: Implemented Local Layout Effect (LLE)-aware STA methodology for advanced nodes using Gate-All-Around (GAA) transistors.
- Developed and maintained STA flows for general foundry customers from 130nm to 2nm tech nodes.
- Estimated timing margins for foundry customers and IP designers.
- Accounting for On-chip variation (IR drop, thermal gradients, process variations and aging.)
Designed a timing estimation engine for full custom digital designs and developed a timing-aware functional verification flow using Verilog